# MULPD
# Multiply Packed Double-Precision Floating-Point Values
Opcode | Mnemonic | Description |
---|---|---|
66 0F 59 /r | MULPD xmm1, xmm2/m128 | Multiply packed double-precision floating-point values in xmm2/m128 by xmm1. |
# Description
Performs an SIMD multiply of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 11-3 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of an SIMD double-precision floating-point operation.
# Operation
Destination[0..63] = Destination[0..63] * Source[0..63];
Destination[64..127] = Destination[64..127] * Source[64..127];
1
2
3
2
3
# SIMD Floating-Point Exceptions
Overflow, | Underflow, Invalid, Precision, Denormal. |
# Protected Mode Exceptions
# Real-Address Mode Exceptions
# Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code) | For a page fault. |
Instruction | Latency | Throughput | Execution Unit |
---|---|---|---|
CPUID | 0F3n/0F2n | 0F3n/0F2n | 0F2n |
MULPD xmm, xmm | 7/6 | 2/2 | FP_MUL |