x86 Instruction Set Reference

# DEC

# Decrement by 1

Opcode Mnemonic Description
FE /1 DEC r/m8 Decrement r/m8 by 1.
FF /1 DEC r/m16 Decrement r/m16 by 1.
FF /1 DEC r/m32 Decrement r/m32 by 1.
48+rw DEC r16 Decrement r16 by 1.
48+rd DEC r32 Decrement r32 by 1.

# Description

Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.) This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

# Operation

Destination = Destination - 1;
1
2

# Flags affected

The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.

# Protected Mode Exceptions
#GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.
#GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.

# Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

# Virtual-8086 Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
Instruction Latency Throughput Execution Unit
CPUID 0F3n/0F2n 0F3n/0F2n 0F2n
DEC 1/1 0.5/0.5 ALU

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