x86 Instruction Set Reference

# MOVUPD

# Move Unaligned Packed Double-Precision Floating- Point Values

Opcode Mnemonic Description
66 0F 10 /r MOVUPD xmm1, xmm2/m128 Move packed double-precision floating-point values from xmm2/m128 to xmm1.
66 0F 11 /r MOVUPD xmm2/m128, xmm Move packed double-precision floating-point values from xmm1 to xmm2/m128.

# Description

Moves a double quadword containing two packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, store the contents of an XMM register into a 128-bit memory location, or move data between two XMM registers. When the source or destination operand is a memory operand, the operand may be unaligned on a 16- byte boundary without causing a general-protection exception (#GP) to be generated.

To move double-precision floating-point values to and from memory locations that are known to be aligned on 16-byte boundaries, use the MOVAPD instruction.

While executing in 16-bit addressing mode, a linear address for a 128-bit data access that overlaps the end of a 16-bit segment is not allowed and is defined as reserved behavior. A specific processor implementation may or may not generate a general-protection exception (#GP) in this situation, and the address that spans the end of the segment may or may not wrap around to the beginning of the segment.

# Operation

Destination = Source;
1
2

# SIMD Floating-Point Exceptions

None.

# Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If TS in CR0 is set.

# Real-Address Mode Exceptions
#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.
#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM If TS in CR0 is set.

# Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode
#PF(fault-code) For a page fault.
Instruction Latency Throughput Execution Unit
CPUID 0F3n/0F2n 0F3n/0F2n 0F2n
MOVUPD xmm, xmm 6/6 1/1 FP_MOVE

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